The power consumption of an electronic circuit system depends upon the power supply voltage and the clock frequency for operating the system, that is, increases in proportion to the square of the power supply voltage and to the frequency of the clock. However, the operation state or the load situation is not fixed with an information processing apparatus such as a computer. An architecture of a system is known wherein the system state changes such that, for example, when the system has a task to process, it operates, but when it has no other task to process after the process of the task comes to an end, the system enters a standby state.
Several methods are known wherein an operation state of a system is observed and a clock or the like is controlled to reduce wasteful power consumption. According to one of the methods, the clock frequency is decreased when it is detected that the system enters a standby state as disclosed, for example, in Japanese Patent Laid-Open No. Hei 11-219237 (hereinafter referred to as Patent Document 1). According to another one of the methods, the load situation of a bus is measured to calculate a bus access rate within a predetermined period of time, and the clock is changed over between different clocks in response to the access rate as disclosed, for example, in Japanese Patent Laid-Open No. Hei 11-184554 (hereinafter referred to as Patent Document 2).
The method of the Patent Document 1, however, has a problem in that, where a system frequently repeats a transition between a standby state and an operation state, it is necessary to perform a changeover process of the clock frequency every time. The method of the Patent Document 2 has another problem in that a circuit for supervising the load situation of a bus is required and also in that-it is not sufficiently high in flexibility in that the load situation of the bus and the load situation of the system do not always coincide with each other. Therefore, the assignee of the present patent application has proposed an architecture which provides a high flexibility and can reduce the load to the system as a countermeasure against the problems of the related art methods described above. According to the architecture, the clock frequency can be changed automatically in response to a ratio of the operation state of the system, and an optimum control is used in response to an activity (a ratio with which a target circuit is in an operation state within a predetermined period of time) to minimize the power consumption of the system.
The architecture described above, however, has a problem in the degree of freedom in design in regard to control for determining an operation frequency appropriate to an operation state of a system.
For example, where an architecture which includes an observation circuit or a like circuit for supervising an operation state of a target circuit, that is, an object of frequency control includes a hardware configuration for calculating an optimum clock frequency through fixed circuit calculation from a result of the observation of the clock frequency, it is difficult to control the frequency paying sufficient attention to the accuracy, a characteristic of a load itself and so forth. It is estimated that various tasks are processed by a system (computer equipment and so forth) including a task of a type which should be completed as early as possible at any rate such as, for example, an ordinary calculation process and search process and a task of another type which imposes only a fixed load and need not necessarily be completed early such as, for example, reproduction of music or moving pictures. Therefore, it is almost impossible to implement a configuration for determining an optimum frequency for all of the task types. Or, since a configuration or process which is much complicated in mounting of hardware is inevitably required, the architecture described above has a problem in terms of the cost and the design. In particular although it is necessary to determine an optimum operation frequency in response to a situation which varies every moment in order to make it possible to effect augmentation of the performance and power-saving to be exhibited through control of the operation frequency of the control object, it sometimes becomes necessary to change the point of view of frequency determination or the algorithm in response to various situations or it is sometimes obliged to make an extensive design change. For example, it is obliged to make a devise for control logic.